1. Field of the Invention
The present invention relates to a semiconductor memory apparatus, particularly to a semiconductor integrated circuit apparatus including a nonvolatile memory cell transistor and select transistor. Moreover, the apparatus is used, for example, in a semiconductor memory or memory embedded device which includes a NAND type memory array.
2. Description of the Related Art
In recent years, an electrically erasable and programmable read only memory (EEPROM) which is electrically writable/erasable has remarkably spread. A conventional structure of EEPROM will be described with reference to FIG. 1. FIG. 1 is a sectional view along a bit line direction in a memory cell array region of a NAND type flash memory.
As shown, two select transistors ST1, ST2 and n memory cell transistors MC1 to MCn connected in series between the select transistors are formed in a memory cell array. Each of the transistors ST1, ST2, MC1 to MCn includes a multi-layer gate formed on a silicon substrate 100 with a gate insulating film (tunnel insulating film) 110 interposed therebetween. The gate insulating film 110 is thin to such an extent that a tunnel current can flow. The multi-layer gate includes: a charge accumulation layer 120 electrically separated for each memory cell; a control gate 130; a inter-gate insulating film 140 formed between the charge accumulation layer 120 and control gate 130; and a gate cap film 150 disposed on the control gate 130. In the silicon substrate 100 on both sides of the multi-layer gate, n-type impurity diffusion layers 160 having a conductive type opposite to a type of the silicon substrate 100 in which a channel region is formed are formed. The impurity diffusion layer 160 functions as a source, drain region. The selection and memory cell transistors are formed including the multi-layer gate and impurity diffusion layer 160. Moreover, two select transistors ST1, ST2 and n memory cell transistors MC1 to MCn constituted as described above are connected in series and disposed so that the impurity diffusion layer 160 is shared.
An insulating film 170 is formed on the multi-layer gate, and a contact barrier film 180 is formed on the insulating film 170. Moreover, an interlayer insulating film 190 is formed on the contact barrier film 180. Further in the interlayer insulating film 190, a bit line contact plug 200 and common source line contact plug 210 are formed to reach the drain and source regions of the select transistors ST1, ST2. Additionally, a metal wiring layer 220 is formed on the interlayer insulating film 190. A part of the metal wiring layer 220 is connected to the common source line contact plug 210, and functions as a common source line. Furthermore, an interlayer insulating film 230 is formed on the interlayer insulating film 190, and a metal wiring layer 240 is formed on the interlayer insulating film 230. The metal wiring layer 240 is connected to the bit line contact plug 200 via a contact plug 250, and functions as a bit line. Additionally, the charge accumulation layer 120 and control gate 130 of the select transistor are electrically connected in a region (not shown).
In the flash memory constituted as described above, the charge accumulation layer and semiconductor substrate transmit/receive electric charges with each other via the gate insulating film, so that data is rewritten.
However, in the conventional semiconductor memory device, when the number of rewritings of data increases, the electric charge is trapped in the gate insulating film. Then, the data is reversed by de-trapping the trapped electric charge, and reliability of the memory cell is deteriorated. Particularly, in the flash memory of a type such that the semiconductor substrate is positively biased with respect to the charge accumulation layer and thereby the data is rewritten, this tendency is remarkable. In this type of flash memory, electrons are discharged from the charge accumulation layer using Fowler Nordheim (FN) tunnel current. As a result, the data is rewritten. In this case, an electric field is concentrated particularly in an edge of the charge accumulation layer. Therefore, as compared with the gate insulating film on a channel region, in the gate insulating film in the vicinity of the charge accumulation layer edge, electron trap easily occurs. Furthermore, when a gate length shortens with miniaturization of a semiconductor apparatus, there is a tendency of an increase of an influence in the vicinity of the charge accumulation layer edge with respect to the channel region. As a result, the deterioration of reliability of the memory cell becomes more remarkable.
Moreover, as shown in FIG. 1, the bit line contact plug 200 and common source line contact plug 210 are formed in a self-aligning mariner with respect to the gate electrodes of the select transistors ST1, ST2. In this case, short circuit tends to easily occur between the gate electrode 120 and bit line contact plug 200 of the select transistor ST1, or between the gate electrode 120 and common source line contact plug 210 of the select transistor ST2.